專利授權區國立清華大學國際產學營運總中心 Operations Center for Industry Collaboration

搜尋專利授權區

關鍵字

» 新增關鍵字

選單

專利授權區

專利授權區
專利名稱(中)	Differential Sensing and TSV Timing Control Scheme for 3D-IC
專利名稱(英)	三維晶片之差動感測及矽晶穿孔時序控制結構
專利家族	中華民國：I441190 美國：7,969,193
專利權人	國立清華大學 100%
發明人	陳炎輝,吳威震,張孟凡
技術領域	電子電機

專利摘要(中)
This disclosure uses a differential sensing and TSV timing control scheme for 3D-IC, which includes a first chip layer of the stacked device having a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal line, a first differential signal driver is coupled to the sensing circuit, horizontally. The Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer. The Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N-2) TSVs to act as dummy loadings. The TSV and (N-2) TSVs penetrate the stacked device from Nth chip layer to first chip layer. The TSV shares same configuration with the (N-2) TSVs. The Nth differential signal driver is vertically coupled to the first differential signal driver through a pair of TSVs and (N-2) pairs of TSVs, vertically. The pair of TSVs and the (N-2) TSVs penetrate the stacked device from the Nth chip layer to the first chip layer. Each of TSV is formed between a first and a second chip layers. Each of TSV is formed between any adjacent two chip layers of the stacked device.

專利摘要(中)

This disclosure uses a differential sensing and TSV timing control scheme for 3D-IC, which includes a first chip layer of the stacked device having a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal line, a first differential signal driver is coupled to the sensing circuit, horizontally. The Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer. The Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N-2) TSVs to act as dummy loadings. The TSV and (N-2) TSVs penetrate the stacked device from Nth chip layer to first chip layer. The TSV shares same configuration with the (N-2) TSVs. The Nth differential signal driver is vertically coupled to the first differential signal driver through a pair of TSVs and (N-2) pairs of TSVs, vertically. The pair of TSVs and the (N-2) TSVs penetrate the stacked device from the Nth chip layer to the first chip layer. Each of TSV is formed between a first and a second chip layers. Each of TSV is formed between any adjacent two chip layers of the stacked device.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw