教師研發能量專區國立清華大學國際產學營運總中心 Operations Center for Industry Collaboration

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基本資料
教授姓名	張孟凡
學系	電機工程學系
職稱	教授

專利
DYNAMIC GRADIENT CALIBRATION METHOD FOR COMPUTING-IN-MEMORY NEURAL NETWORK AND SYSTEM THEREOF
INPUT-SHAPING METHOD AND INPUT-SHAPING UNIT FOR GROUP-MODULATED INPUT SCHEME IN COMPUTING-IN-MEMORY APPLICATIONS
MEMORY UNIT WITH MULTI-BIT INPUT LOCAL COMPUTING CELL FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS, MEMORY ARRAY STRUCTURE WITH MULTI-BIT INPUT LOCAL COMPUTING CELL FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMP
MEMORY UNIT WITH MULTIPLY-ACCUMULATE ASSIST SCHEME FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
MEMORY UNIT FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS, MEMORY ARRAY STRUCTURE FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD
QUANTIZATION METHOD FOR PARTIAL SUMS OF CONVOLUTION NEURAL NETWORK BASED ON COMPUTING-IN-MEMORY HARDWARE AND SYSTEM THEREOF
MEMORY STRUCTURE WITH INPUT-AWARE MAXIMUM MULTIPLY-AND-ACCUMULATE VALUE ZONE PREDICTION FOR COMPUTING-IN-MEMORY APPLICATIONS AND OPERATING METHOD THEREOF
MEMORY UNIT WITH ASYMMETRIC GROUP-MODULATED INPUT SCHEME AND CURRENT-TO-VOLTAGE SIGNAL STACKING SCHEME FOR NON-VOLATILE COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
TRANSPOSE MEMORY UNIT FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS,TRANSPOSE MEMORY ARRAY STRUCTURE FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
MEMORY UNIT WITH MULTIPLE WORD LINES FOR NONVOLATILE COMPUTING-IN-MEMORY APPLICATIONS AND CURRENT CALIBRATING METHOD THEREOF
MEMORY UNIT WITH ADAPTIVE CLAMPING VOLTAGE SCHEME AND CALIBRATION SCHEME FOR MULTI-LEVEL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
METHOD AND SYSTEM FOR PERFORMING PHYSICAL UNCLONABLE FUNCTION GENERATED BY NON-VOLATILE MEMORY WRITE DELAY DIFFERENCE
MULTI-BIT CURRENT SENSE AMPLIFIER WITH PIPELINE CURRENT SAMPLING OF RESISTIVE MEMORY ARRAY STRUCTURE AND SENSING METHOD THEREOF
MEMORY DEVICE
SENSING CIRCUIT WITH ADAPTIVE LOCAL REFERENCE GENERATION OF RESISTIVE MEMORY AND SENSING METHOD THEREOF
VOLTAGE-ENHANCED-FEEDBACK SENSE AMPLIFIER OF RESISTIVE MEMORY AND OPERATING METHOD THEREOF
MEMORY CELL FOR COMPUTING-IN-MEMORY APPLICATIONS,MEMORY UNIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
CONTROL CIRCUIT CONFIGURED TO TERMINATE A SET OPERATION AND A RESET OPERATION OF A RESISTIVE MEMORY CELL OF MEMORY ARRAY BASED ON THE VOLTAGE VARIATION ON THE DATA LINE OF THE RESISTIVE MEMORY CELL
SOFT-VERIFY WRITE ASSIST CIRCUIT OF RESISTIVE MEMORY AND OPERATING METHOD THEREOF
DYNAMIC BIT-LINE CLAMPING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND CLAMPING METHOD THEREOF
REFERENCE-FREE MULTI-LEVEL SENSING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS, REFERENCE-FREE MEMORY UNIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND SENSING METHOD THEREOF
MULTI-BIT COMPUTING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
INPUT-PATTERN AWARE REFERENCE GENERATION SYSTEM AND COMPUTING-IN-MEMORY SYSTEM INCLUDING THE SAME
SELECTIVE BIT-LINE SENSING METHOD AND STORAGE DEVICE UTILIZING THE SAME
TRANSPOSE ACCESSING MEMORY DEVICE AND METHOD
METHOD AND CIRCUIT FOR GENERATING A REFERENCE VOLTAGE IN NEUROMORPHIC SYSTEM
CONTROL CIRCUIT CONFIGURED TO TERMINATE A SET OPERATION AND A RESET OPERATION OF A RESISTIVE MEMORY CELL OF MEMORY ARRAY BASED ON THE VOLTAGE VARIATION ON THE DATA LINE OF THE RESISTIVE MEMORY CELL
SENSING CIRCUIT, SET OF PRE-AMPLIFIERS, AND OPERATING METHOD THEREOF
SENSE AMPLIFIER OF RESISTIVE MEMORY AND OPERATING METHOD THEREOF
Memory apparatus and write failure responsive negative bitline voltage write assist circuit thereof
TERNARY CONTENT ADDRESSABLE MEMORY
NON-VOLATILE LATCH
6T STATIC RANDOM ACCESS MEMORY CELL, ARRAY AND MEMORY THEREOF/6T STATIC RANDOM ACCESS MEMORY CELL, ARRAY AND MEMORY THEREOF
NON-VOLATILE STATIC RANDOM ACCESS MEMORY USING A 7T1R CELL WITH INITIALIZATION AND PULSE OVERWRITE
NON-VOLATILE TERNARY CONTENT-ADDRESSABLE MEMORY WITH BI-DIRECTIONAL VOLTAGE DIVIDER CONTROL AND MULTI-STEP SEARCH
TERNARY CONTENT-ADDRESSABLE MEMORY/TERNARY CONTENT-ADDRESSABLE MEMORY
MEMORY APPARATUS
SENSE AMPLIFIER
SENSE AMPLIFIER
Non-Volatile Ternary Content-Addressable Memory with Resistive Memory Device
Scheme for 3D Voltage Type TSV Signal Transmission
6T STATIC RANDOM ACCESS MEMORY CELL, ARRAY AND MEMORY THEREOF
Non-volatile Ternary Content-Addressable Memory 4T2R cell with RC-delay search
Sensing marging expanding scheme for memory
3D-IC Differential Sensing and Charge Sharing Scheme
利用電容耦合實現動態參考電壓之感測放大器
三維晶片之差動感測及電荷共享架構
基極驅動電流感測放大器及其操作方法
低飄移偏差之電流感測放大器及其操作方法
Control Scheme for 3D memory IC
6T STATIC RANDOM ACCESS MEMORY CELL, ARRAY AND MEMORY THEREOF
三维芯片之不连续型态层识别编号检测器及其方法
三維記憶體晶片之控制結構
SENSING AMPLIFIER USING CAPACITIVE COUPLING TO REALIZE DYNAMIC REFERENCE VOLTAGE
PULSE TYPE LAYER-ID DETECTOR FOR 3D-IC AND METHOD OF THE SAME
三維晶片之突波型態層識別編號檢測器及其方法
三維晶片之差動感測及矽晶穿孔時序控制結構
Layer-ID Detector for Multilayer 3D-IC and Method of the Same
用于低供应电压的电子泵
Current Mirror Modified Level Shifter
三维芯片之突波型态层识别编号检测器
Discontinuous Type Layer-ID Detector for 3D-IC and Method of the Same
LOW-OFFSET CURRENT-SENSE AMPLIFIER AND OPERATING METHOD THEREOF
STATIC RANDOM ACCESS MEMORY CELL
Charge pump system for low-supply voltage
BULK DRIVEN CURRENT SENSE AMPLIFIER AND OPERATING METHOD THEREOF
CURRENT-SENSE AMPLIFIER WITH LOW-OFFSET ADJUSTMENT AND METHOD OF LOW-OFFSET ADJUSTMENT THEREOF
CHARGE PUMP WITH LOW NOISE AND HIGH OUTPUT CURRENT AND VOLTAGE
REFERENCE CURRENT GENERATOR FOR RESISTANCE TYPE MEMORY AND METHOD
Offset Cancellation Current Mirror and Operating Method Thereof
Current Sensing Amplifier and Method Thereof
MEMORY REFRESH SYSTEM AND OPERATING METHOD THEREOF
用於一靜態隨機存取記憶體之存取單元
Differential Sensing and TSV Timing Control Scheme for 3D-IC
Dual Mode Accessing Signal Control Apparatus and Dual Mode Timing Signal Generating Apparatus
Access Unit for a Static Random Access Memory
MEMORY UNIT WITH TIME DOMAIN EDGE DELAY ACCUMULATION FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
MEMORY ARRAY STRUCTURE WITH DYNAMIC DIFFERENTIAL-REFERENCE BASED READOUT SCHEME FOR COMPUTING-IN-MEMORY APPLICATIONS, DYNAMIC DIFFERENTIAL-REFERENCE TIME-TO-DIGITAL CONVERTER FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
INPUT SEQUENCE RE-ORDERING METHOD AND INPUT SEQUENCE RE-ORDERING UNIT WITH MULTI INPUT-PRECISION RECONFIGURABLE SCHEME AND PIPELINE SCHEME FOR COMPUTING-IN-MEMORY MACRO IN CONVOLUTIONAL NEURAL NETWORK APPLICATION
MEMORY UNIT FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS BASED ON CHARGE SHARING, MEMORY ARRAY STRUCTURE FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS BASED ON CHARGE SHARING AND COM