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專利授權區

專利授權區
專利名稱(中)	基於記憶體內運算單元之軟硬體協同之壓縮運算方法及其系統
專利名稱(英)	HARDWARE/SOFTWARE CO-COMPRESSED COMPUTING METHOD AND SYSTEM FOR SRAM COMPUTING-IN-MEMORY-BASED PROCESSING UNIT
專利家族	中華民國：I769807 美國：2022-0366971(公開號)
專利權人	國立清華大學 100%
發明人	鄭桂忠,謝軒顥,李杰倫
技術領域	電子電機

專利摘要(英)
A hardware/software co-compressed computing method for a SRAM Computing-in-memory-based (CIM-based) processing unit is proposed. The hardware/software co-compressed computing method for the SRAM CIM-based processing unit includes a data dividing step, a sparsity step, an address assigning step and a hardware decoding and calculating step. The data dividing step is performed to divide a plurality of kernels corresponding to an input feature map into a plurality of weight groups. The sparsity step includes a weight setting step. The weight setting step is performed to set each of the weight groups to one of a zero weight group and a non-zero weight group according to a sparsity aware computing method. The address assigning step is performed to assign a plurality of index codes to a plurality of the non-zero weight groups of the kernels, respectively. The hardware decoding and calculating step is performed to execute an inner product to the non-zero weight group and the input feature data group corresponding to the non-zero weight group, and generate an output feature data group. Thus, the hardware/software co-compressed computing method and system for the SRAM CIM-based processing unit compress the computing data volume computed by the SRAM CIM-based accelerators, and increase the computing speed.

專利摘要(英)

A hardware/software co-compressed computing method for a SRAM Computing-in-memory-based (CIM-based) processing unit is proposed. The hardware/software co-compressed computing method for the SRAM CIM-based processing unit includes a data dividing step, a sparsity step, an address assigning step and a hardware decoding and calculating step. The data dividing step is performed to divide a plurality of kernels corresponding to an input feature map into a plurality of weight groups. The sparsity step includes a weight setting step. The weight setting step is performed to set each of the weight groups to one of a zero weight group and a non-zero weight group according to a sparsity aware computing method. The address assigning step is performed to assign a plurality of index codes to a plurality of the non-zero weight groups of the kernels, respectively. The hardware decoding and calculating step is performed to execute an inner product to the non-zero weight group and the input feature data group corresponding to the non-zero weight group, and generate an output feature data group. Thus, the hardware/software co-compressed computing method and system for the SRAM CIM-based processing unit compress the computing data volume computed by the SRAM CIM-based accelerators, and increase the computing speed.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw