| Provided is a semiconductor power device including a substrate having a circuit region and a power device region, a buffer layer, a nitride channel layer, a barrier layer, a power transistor and a complementary logic circuit. The buffer layer is disposed on the substrate. The nitride channel layer is disposed on the buffer layer. The barrier layer is disposed on the nitride channel layer. The power transistor is disposed on the substrate in the power device region. The complementary logic circuit is disposed on the substrate in the circuit region and electrically connected to the power transistor, and includes a P-type transistor and an N-type transistor. The P-type transistor includes a 2D material channel layer. The N-type transistor is electrically connected to the P-type transistor. A 2DEG is located in the nitride channel layer and adjacent to an interface between the nitride channel layer and the barrier layer. |