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專利授權區

專利授權區
專利名稱(中)	半導體功率元件
專利名稱(英)	SEMICONDUCTOR POWER DEVICE
專利家族	中華民國：I871138
專利權人	國立清華大學 100.00%
發明人	徐碩鴻,黃敬源,葉昭輝
技術領域	通信傳輸,能源科技,電子電機

專利摘要(中)
一種半導體功率元件，其包括基底、緩衝層、氮化物通道層、阻障層、功率電晶體以及互補式邏輯電路。所述基底具有電路區以及功率元件區。所述緩衝層設置於所述基底上。所述氮化物通道層設置於所述緩衝層上。所述阻障層設置於所述氮化物通道層上。所述功率電晶體設置於所述功率元件區中的所述基底上。所述互補式邏輯電路設置於所述電路區中的所述基底上且與所述功率電晶體電性連接，且包括P型電晶體與N型電晶體。所述P型電晶體包括二維材料通道層。所述N型電晶體與所述P型電晶體電性連接。二維電子氣位於所述氮化物通道層中且鄰近所述氮化物通道層與所述阻障層之間的界面。

專利摘要(中)

一種半導體功率元件，其包括基底、緩衝層、氮化物通道層、阻障層、功率電晶體以及互補式邏輯電路。所述基底具有電路區以及功率元件區。所述緩衝層設置於所述基底上。所述氮化物通道層設置於所述緩衝層上。所述阻障層設置於所述氮化物通道層上。所述功率電晶體設置於所述功率元件區中的所述基底上。所述互補式邏輯電路設置於所述電路區中的所述基底上且與所述功率電晶體電性連接，且包括P型電晶體與N型電晶體。所述P型電晶體包括二維材料通道層。所述N型電晶體與所述P型電晶體電性連接。二維電子氣位於所述氮化物通道層中且鄰近所述氮化物通道層與所述阻障層之間的界面。

專利摘要(英)
Provided is a semiconductor power device including a substrate, a buffer layer, a nitride channel layer, a barrier layer, a power transistor and a complementary logic circuit. The substrate has a circuit region and a power device region. The buffer layer is disposed on the substrate. The nitride channel layer is disposed on the buffer layer. The barrier layer is disposed on the nitride channel layer. The power transistor is disposed on the substrate in the power device region. The complementary logic circuit is disposed on the substrate in the circuit region and is electrically connected to the power transistor. The complementary logic circuit includes a P-type transistor and an N-type transistor. The P-type transistor includes a two-dimensional material channel layer. The N-type transistor is electrically connected to the P-type transistor. A two-dimensional electron gas (2DEG) is located in the nitride channel layer adjacent to the interface between the nitride channel layer and the barrier layer.

專利摘要(英)

Provided is a semiconductor power device including a substrate, a buffer layer, a nitride channel layer, a barrier layer, a power transistor and a complementary logic circuit. The substrate has a circuit region and a power device region. The buffer layer is disposed on the substrate. The nitride channel layer is disposed on the buffer layer. The barrier layer is disposed on the nitride channel layer. The power transistor is disposed on the substrate in the power device region. The complementary logic circuit is disposed on the substrate in the circuit region and is electrically connected to the power transistor. The complementary logic circuit includes a P-type transistor and an N-type transistor. The P-type transistor includes a two-dimensional material channel layer. The N-type transistor is electrically connected to the P-type transistor. A two-dimensional electron gas (2DEG) is located in the nitride channel layer adjacent to the interface between the nitride channel layer and the barrier layer.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw