| A feed-forward equalizer is provided.  The feed-forward equalizer includes a shift register, a look-up table circuit, a selection circuit and an output terminal.  The shift register temporarily stores and shifts an input data based on a clock signal to obtain a plurality of shifted input data.  The look-up table circuit has a plurality of processed signals.  The processed signals are obtained by logical operation of a plurality of coefficients.  The input end of the selection circuit is coupled to the look-up table circuit.  A control terminal of the selection circuit receives the shifted input data.  The selection circuit selects at least one of the processed signals of the look-up table circuit as a selected signal based on the shifted input data.  The output terminal provides an output signal according to the selected signal. |