專利授權區國立清華大學國際產學營運總中心 Operations Center for Industry Collaboration

搜尋專利授權區

關鍵字

» 新增關鍵字

選單

專利授權區

專利授權區
專利名稱(中)	類神經網路系統、高密度內嵌式人工突觸元件及其操作方法
專利名稱(英)	NEURAL NETWORK SYSTEM, HIGH DENSITY EMBEDDED-ARTIFICIAL SYNAPTIC ELEMENT AND OPERATING METHOD THEREOF
專利家族	中華民國：I802313 美國：2023-0289577(公開號)
專利權人	國立清華大學 100.00%
發明人	金雅琴,余昕芫,林崇榮
技術領域	電子電機

專利摘要(中)
本發明提供一種高密度內嵌式人工突觸元件，其包含半導體基板、選擇電晶體、金屬層以及記憶電晶體。選擇電晶體設置於半導體基板且包含第一閘極結構、汲極區及源極區。汲極區與源極區分別位於第一閘極結構之相對二側。金屬層連接汲極區。記憶電晶體設置於半導體基板並與選擇電晶體共平面。記憶電晶體包含第二閘極結構、第一電極區、第二電極區、第一憶阻器及第二憶阻器。第二閘極結構連接金屬層。第一憶阻器形成於第二閘極結構與第一電極區之間。第二憶阻器形成於第二閘極結構與第二電極區之間。藉此，達到雙位元的資料密度。

專利摘要(中)

本發明提供一種高密度內嵌式人工突觸元件，其包含半導體基板、選擇電晶體、金屬層以及記憶電晶體。選擇電晶體設置於半導體基板且包含第一閘極結構、汲極區及源極區。汲極區與源極區分別位於第一閘極結構之相對二側。金屬層連接汲極區。記憶電晶體設置於半導體基板並與選擇電晶體共平面。記憶電晶體包含第二閘極結構、第一電極區、第二電極區、第一憶阻器及第二憶阻器。第二閘極結構連接金屬層。第一憶阻器形成於第二閘極結構與第一電極區之間。第二憶阻器形成於第二閘極結構與第二電極區之間。藉此，達到雙位元的資料密度。

專利摘要(英)
The present disclosure provides a high density embedded-artificial synaptic element, which includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure, respectively. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and coplanar with the select transistor. The memory transistor includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region. Therefore, a data density of two bits is achieved.

專利摘要(英)

The present disclosure provides a high density embedded-artificial synaptic element, which includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure, respectively. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and coplanar with the select transistor. The memory transistor includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region. Therefore, a data density of two bits is achieved.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw