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專利授權區

專利授權區
專利名稱(中)	類神經網路系統、高密度內嵌式人工突觸元件及其操作方法
專利名稱(英)	NEURAL NETWORK SYSTEM, HIGH DENSITY EMBEDDED-ARTIFICIAL SYNAPTIC ELEMENT AND OPERATING METHOD THEREOF
專利家族	中華民國：I802313 美國：2023-0289577(公開號)
專利權人	國立清華大學 100%
發明人	金雅琴,余昕芫,林崇榮
技術領域	電子電機

專利摘要(英)
The present disclosure provides a high density embedded-artificial synaptic element, which includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure, respectively. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and coplanar with the select transistor. The memory transistor includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region. Therefore, a data density of two bits is achieved.

專利摘要(英)

The present disclosure provides a high density embedded-artificial synaptic element, which includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure, respectively. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and coplanar with the select transistor. The memory transistor includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region. Therefore, a data density of two bits is achieved.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw