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專利授權區
專利名稱(中)	解碼器、解碼器裝置及接收器
專利家族	中華民國：I882830
專利權人	國立清華大學 100.00%
發明人	彭朋瑞,林彥博
技術領域	通信傳輸,電子電機

專利摘要(中)
一解碼器包括一訊號放大器、一解多工器及多個類比數位轉換器。訊號放大器接收源自PAM-2M格式的一輸入資料訊號的一待放大資料訊號，藉由1＋D脈衝整形將待放大資料訊號轉換為PAM-(2M＋1-1)格式，並對待放大資料訊號執行放大和位準偏移以產生一待解碼資料訊號，其中M≧2。解多工器接收並解多工待解碼資料訊號為多筆解多工資料訊號，以供個別的類比數位轉換器接收。類比數位轉換器其中之一為(M＋2)位元類比數位轉換器並轉換對應的解多工資料訊號為包含(M＋1)位元的資料部分及一位元的誤差部分的第一解碼訊號。其餘的類比數位轉換器為(M＋1)位元類比數位轉換器並轉換對應的解多工資料訊號為包含(M＋1)位元的資料部分的第二解碼訊號。

專利摘要(中)

一解碼器包括一訊號放大器、一解多工器及多個類比數位轉換器。訊號放大器接收源自PAM-2M格式的一輸入資料訊號的一待放大資料訊號，藉由1＋D脈衝整形將待放大資料訊號轉換為PAM-(2M＋1-1)格式，並對待放大資料訊號執行放大和位準偏移以產生一待解碼資料訊號，其中M≧2。解多工器接收並解多工待解碼資料訊號為多筆解多工資料訊號，以供個別的類比數位轉換器接收。類比數位轉換器其中之一為(M＋2)位元類比數位轉換器並轉換對應的解多工資料訊號為包含(M＋1)位元的資料部分及一位元的誤差部分的第一解碼訊號。其餘的類比數位轉換器為(M＋1)位元類比數位轉換器並轉換對應的解多工資料訊號為包含(M＋1)位元的資料部分的第二解碼訊號。

專利摘要(英)
A decoder includes a signal amplifier, a demultiplexer and multiple ADCs. The signal amplifier receives a to-be-amplified data signal that originated from an input data signal in a PAM-2M format and that is in a PAM-(2M＋1-1) format because of 1＋D pulse shaping, and performs amplification and level shifting on the to-be-amplified data signal to generate a to-be-decoded data signal, where M2. The demultiplexer receives the to-be-decoded data signal, and demultiplexes the to-be-decoded data signal into multiple demultiplexed data signals to be respectively received by the ADCs. One of the ADCs is an (M＋2)-bit ADC, and converts the corresponding demultiplexed data signal into a first decoded signal containing an (M＋1)-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an (M＋1)-bit ADC, and converts the corresponding demultiplexed data signal into a second decoded signal containing an (M＋1)-bits wide data portion.

專利摘要(英)

A decoder includes a signal amplifier, a demultiplexer and multiple ADCs. The signal amplifier receives a to-be-amplified data signal that originated from an input data signal in a PAM-2M format and that is in a PAM-(2M＋1-1) format because of 1＋D pulse shaping, and performs amplification and level shifting on the to-be-amplified data signal to generate a to-be-decoded data signal, where M2. The demultiplexer receives the to-be-decoded data signal, and demultiplexes the to-be-decoded data signal into multiple demultiplexed data signals to be respectively received by the ADCs. One of the ADCs is an (M＋2)-bit ADC, and converts the corresponding demultiplexed data signal into a first decoded signal containing an (M＋1)-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an (M＋1)-bit ADC, and converts the corresponding demultiplexed data signal into a second decoded signal containing an (M＋1)-bits wide data portion.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw