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專利授權區
專利名稱(中)	基於混合精度演算法和記憶體內運算加速器之軟硬體協同運作方法及其系統及非暫態電腦可讀儲存媒體
專利名稱(英)	HARDWARE AND SOFTWARE CO-DESIGN METHOD WITH MIXED-PRECISION ALGORITHM AND COMPUTING-IN-MEMORY-BASED ACCELERATOR AND SYSTEM THEREOF, AND NON-TRANSITORY COMPUTER READABLE STORGE MEDIUM
專利家族	中華民國：I884041
專利權人	國立清華大學 100.00%
發明人	鄭桂忠,陳彥文,王睿瑄,鄭宇翔,盧峙丞,張孟凡
技術領域	電子電機

專利摘要(中)
本發明提供一種基於混合精度演算法和記憶體內運算加速器之軟硬體協同運作系統，其處理器從記憶體獲得預訓練模型之初始權重參數；針對初始權重參數進行剪枝程序，以產生剪枝權重；及針對剪枝權重的非零權重進行濾波器混合精度量化訓練而產生具有不同位元寬度之濾波器權重，並將濾波器權重進行配對而產生成對的濾波器權重組，並將成對的濾波器權重組進行混合而產生混合精度權重。記憶體內運算加速器針對混合精度權重及輸入參數執行記憶體內運算而產生記憶體內運算輸出。藉此，可以充分運算混合精度網路，並提升CIM的利用率及運算速度。

專利摘要(中)

本發明提供一種基於混合精度演算法和記憶體內運算加速器之軟硬體協同運作系統，其處理器從記憶體獲得預訓練模型之初始權重參數；針對初始權重參數進行剪枝程序，以產生剪枝權重；及針對剪枝權重的非零權重進行濾波器混合精度量化訓練而產生具有不同位元寬度之濾波器權重，並將濾波器權重進行配對而產生成對的濾波器權重組，並將成對的濾波器權重組進行混合而產生混合精度權重。記憶體內運算加速器針對混合精度權重及輸入參數執行記憶體內運算而產生記憶體內運算輸出。藉此，可以充分運算混合精度網路，並提升CIM的利用率及運算速度。

專利摘要(英)
A hardware and software co-design system with a mixed-precision algorithm and a compute-in-memory(CIM)-based accelerator includes a memory, a processor and the CIM-based accelerator. The memory stores a plurality of sets of initial weight parameters of a pre-trained model and a plurality of sets of input parameters. The processor is electrically connected to the memory. The processor is configured to perform operations including performing an initial weight obtaining operation, a pruning quantization joint training operation and a mixed-precision quantization operation. The initial weight obtaining operation includes obtaining the sets of initial weight parameters of the pre-trained model from the memory. The pruning quantization joint training operation includes performing a pruning procedure on the sets of initial weight parameters to generate a plurality of sets of pruned weights. The mixed-precision quantization operation includes performing a filter-wise mixed-precision quantization training on a plurality of non-zero weights of the sets of pruned weights to generate a plurality of filter weights with different bit widths, and pairing the filter weights to generate a plurality of paired filter weight groups, and mixing the paired filter weight groups to generate a plurality of mixed-precision weights. The CIM-based accelerator is electrically connected to the memory and the processor, and receives the mixed-precision weights and the sets of input parameters. The CIM-based accelerator performs a CIM operation on the mixed-precision weights and the sets of input parameters to generate a plurality of CIM outputs. Therefore, the hardware and software co-design system with the mixed-precision algorithm and the CIM-based accelerator of the present disclosure can enable full-scale computations for mixed-precision networks and enhance utilization rates and computational speed.

專利摘要(英)

A hardware and software co-design system with a mixed-precision algorithm and a compute-in-memory(CIM)-based accelerator includes a memory, a processor and the CIM-based accelerator. The memory stores a plurality of sets of initial weight parameters of a pre-trained model and a plurality of sets of input parameters. The processor is electrically connected to the memory. The processor is configured to perform operations including performing an initial weight obtaining operation, a pruning quantization joint training operation and a mixed-precision quantization operation. The initial weight obtaining operation includes obtaining the sets of initial weight parameters of the pre-trained model from the memory. The pruning quantization joint training operation includes performing a pruning procedure on the sets of initial weight parameters to generate a plurality of sets of pruned weights. The mixed-precision quantization operation includes performing a filter-wise mixed-precision quantization training on a plurality of non-zero weights of the sets of pruned weights to generate a plurality of filter weights with different bit widths, and pairing the filter weights to generate a plurality of paired filter weight groups, and mixing the paired filter weight groups to generate a plurality of mixed-precision weights. The CIM-based accelerator is electrically connected to the memory and the processor, and receives the mixed-precision weights and the sets of input parameters. The CIM-based accelerator performs a CIM operation on the mixed-precision weights and the sets of input parameters to generate a plurality of CIM outputs. Therefore, the hardware and software co-design system with the mixed-precision algorithm and the CIM-based accelerator of the present disclosure can enable full-scale computations for mixed-precision networks and enhance utilization rates and computational speed.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw