專利授權區國立清華大學國際產學營運總中心 Operations Center for Industry Collaboration

搜尋專利授權區

關鍵字

» 新增關鍵字

選單

專利授權區

專利授權區
專利名稱(中)	SENSE AMPLIFIER OF RESISTIVE MEMORY AND OPERATING METHOD THEREOF
專利名稱(英)	SENSE AMPLIFIER OF RESISTIVE MEMORY AND OPERATING METHOD THEREOF
專利家族	美國：10,186,318
專利權人	國立清華大學 100%
發明人	楊子賢,張孟凡
技術領域	電子電機

專利摘要(中)
A sense amplifier of a resistive memory is controlled by a bit line and a reference line. A voltage sense amplifier has a bit-line input node and a reference input node. A margin enhanced pre-amplifier includes a bit-line two-terminal switching element, a bit-line capacitor, a bit-line three-terminal switching element, a reference two-terminal switching element, a reference capacitor and a reference three-terminal switching element. A read voltage difference between the voltage level of the bit line and the reference line is generated. The bit-line two-terminal switching element, the bit-line three-terminal switching element, the reference two-terminal switching element and the reference three-terminal switching element are synchronizedly switched so as to generate a margin enhanced difference between the voltage level of the bit-line input node and the voltage level of the reference input node. The margin enhanced difference is equal to or greater than three times the read voltage difference.

專利摘要(中)

A sense amplifier of a resistive memory is controlled by a bit line and a reference line. A voltage sense amplifier has a bit-line input node and a reference input node. A margin enhanced pre-amplifier includes a bit-line two-terminal switching element, a bit-line capacitor, a bit-line three-terminal switching element, a reference two-terminal switching element, a reference capacitor and a reference three-terminal switching element. A read voltage difference between the voltage level of the bit line and the reference line is generated. The bit-line two-terminal switching element, the bit-line three-terminal switching element, the reference two-terminal switching element and the reference three-terminal switching element are synchronizedly switched so as to generate a margin enhanced difference between the voltage level of the bit-line input node and the voltage level of the reference input node. The margin enhanced difference is equal to or greater than three times the read voltage difference.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw