專利授權區國立清華大學國際產學營運總中心 Operations Center for Industry Collaboration

搜尋專利授權區

關鍵字

» 新增關鍵字

選單

專利授權區

專利授權區
專利名稱(英)	ELECTRONIC DEVICE WITH FAULT AND SOFT ERROR TOLERANT DELAY-LOCKED LOOPS
專利家族	中華民國：I761984 美國：11,190,192
專利權人	國立清華大學 100%
發明人	黃錫瑜,楊竣宇
技術領域	電子電機

專利摘要(中)
自行申請補件

專利摘要(英)
An electronic device includes three delay-locked loops, three dummy voter circuits, and a voter circuit. Each of the three delay-locked loops has a first input end, a second input end, an output end to maintain the phase difference between the reference clock signal received from the first input end and the intermediate clock signal output from the output end. Each of the three voter circuits is connected between the second input end and the output end of each of the three delay-locked loops to delay the phase of the intermediate clock signal by the phase difference. The voter circuit receives the intermediate clock signal from each of the three delay-locked loops, and outputs an output clock signal according to the logic of the intermediate clock signal from each of the three delay-locked loops. The phase difference compensates for the phase delay of the intermediate clock signal passing through the voter circuit.

專利摘要(英)

An electronic device includes three delay-locked loops, three dummy voter circuits, and a voter circuit. Each of the three delay-locked loops has a first input end, a second input end, an output end to maintain the phase difference between the reference clock signal received from the first input end and the intermediate clock signal output from the output end. Each of the three voter circuits is connected between the second input end and the output end of each of the three delay-locked loops to delay the phase of the intermediate clock signal by the phase difference. The voter circuit receives the intermediate clock signal from each of the three delay-locked loops, and outputs an output clock signal according to the logic of the intermediate clock signal from each of the three delay-locked loops. The phase difference compensates for the phase delay of the intermediate clock signal passing through the voter circuit.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw